1. Field of the Invention
The present invention relates to a digital modulation circuit, a digital modulation method, a digital demodulation circuit and a digital demodulation method. More specifically, the present invention relates to a digital modulation circuit and a digital modulation method for modulating an unknown data sequence to a recording signal waveform sequence or channel sequence to be recorded on a recording medium, and to a digital demodulation circuit and a digital demodulation method for demodulating the signal waveform sequence to a data sequence.
2. Description of the Related Art
A binary data sequence is modulated to an appropriate recording signal waveform sequence and recorded on a recording medium. For example, a binary data sequence is subjected to RLL coding and further to NRZI modulation to be recorded on the recording medium. This enhances recording density. The binary data sequence may sometimes be directly subjected to NRZ modulation or NRZI modulation to be recorded on the recording medium.
In RLL coding, datawords of m bits each are successively cut out from an input data sequence, and each dataword is translated to a codeword each of n bits. This translation has a condition for enlarging a minimum value Tmin and reducing a maximum value Tmax of a time interval between adjacent transitions of the NRZI modulated recording signal. More specifically, there is a condition that in the RLL coded code sequence, the number of bits of xe2x80x9c0xe2x80x9d existing between a bit xe2x80x9c1xe2x80x9d and another bit xe2x80x9c1xe2x80x9d must be at least d and at most k. The RLL code translated to satisfy the condition is referred to as (d, k; m, n) RLL code.
In NRZI modulation, an RLL code is modulated such that bit xe2x80x9c1xe2x80x9d is inverted and bit xe2x80x9c0xe2x80x9d is not inverted. Accordingly, bit inversion interval in the signal to be recorded after NRZI modulation becomes wider than the bit inversion interval in the RLL code before NRZI modulation. Therefore, as compared with when the RLL code before NRZI modulation is recorded on a recording medium and reproduced, waveform distortion in the reproduced signal can be reduced when the recording signal after NRZI modulation is recorded on the recording medium and reproduced, and as a result, error in reading can be reduced. When error in recording of approximately the same extent is tolerable, higher recording density can be attained when the recording signal after NRZI modulation is recorded on the recording medium, than when the recording signal before NRZI modulation is on the recording medium.
Desired features of the recording signal waveform sequence are as follows.
(1) Minimum value Tmin of the time interval between adjacent transition of the recording signal
Tmin is calculated as a product of xe2x80x9cd+1xe2x80x9d and duration of channel bit, that is, a detection widow width Tw. When recording density is made higher, inversion interval of recording signals becomes smaller, so that the reproduced signals are more susceptible to distortion because of intersymbol interference. As a result, error in reading is more likely. In order to reduce waveform distortion in reading from a recording medium with high recording density and to reduce error in recording, larger Tmin is desirable.
(2) Maximum value Tmax of the time interval between adjacent transitions of the recording signal
Tmax is calculated as a product of xe2x80x9ck+1xe2x80x9d and the detection window width Tw. A reproduction pulse cannot be obtained unless the polarity is inverted. Therefore, a clock cannot be directly generated from the reproduction pulse, which leads to clocks of lower accuracy. When the interval of polarity inversion becomes longer, there will be much fluctuation in DC component, and therefore smaller Tmax is desirable.
(3) DC component or constant frequency component
A recording apparatus and a reproducing apparatus have an AC coupling device. Therefore, when the recording signal has a DC component, recording signal waveform is distorted in the AC coupling device, which is not desirable. Further, it is not possible to recover in reproduction the DC component lost at the time of recording. Therefore, less DC component and less low frequency component are desired.
For evaluation of the DC component and the low frequency component in the recording signal, DSV (digital Sum Value) is used. DSV represents an accumulated value calculated from the start point of the waveform sequence of the recording signal, with the value of bit xe2x80x9c1xe2x80x9d regarded as xe2x80x9c+1xe2x80x9d and the value of bit xe2x80x9c0xe2x80x9d as xe2x80x9cxe2x88x921xe2x80x9d. If the absolute value of DSV is small, it means that the DC component or the low frequency component is small. For evaluation of the DC component and the low frequency component of each code, CDS (Codeward Digital Sum) is used. CDS represents DSV in each codeword, and smaller CDS represents smaller DC component or low frequency component of the corresponding codeword.
(4) Detection window width Tw
Detection window width Tw is given by (m/n)T, which represents a time which can be used for detection of a reproduction bit, that is, resolution. Further, the detection window width Tw represents window margin against phase fluctuation of the reproduced signal caused by waveform or intersymbol interference or noise, and larger value is desirable.
(5) Constraint length Lc.
In order to improve Tmin, Tmax and DSV, sometimes coding is performed with reference to preceding and succeeding codewords. The length of the preceding or succeeding codeword referred to at that time is called constraint length Lc. As Lc becomes larger, error propagation becomes larger and circuit configuration becomes more complicated. Therefore, smaller Lc is desired.
Japanese Patent Laying-Open No. 52-128024 discloses a technique for marking Tmin larger and marking Tmax smaller in the recording signal after NRZI modulation. According to this Laid-Open application, by RLL coding in which datawords each of 2 bits are successively cut out from an input data sequence and translated to codewords each of 3 bits, (1, 7; 2, 3) RLL codes are produced. Code sequences of thus produced RLL code are subjected to NRZI modulation. When the condition of d=1 cannot be satisfied, (1, 7; 4, 6) RLL codes are produced.
Japanese Patent Publication No. 1-27510 discloses a technique of coding (RLL coding) for reducing DC component of the recording signal after NRZI modulation is disclosed, in which coding is performed so as not to reduce Tmin of the recording signal after NRZI modulation. According to this published application, blocks each of n bits are successively cut out from a code sequence after coding, and between adjacent blocks, redundancy bits each consisting of a plurality of bits are inserted. The code sequence with redundancy bits inserted is supplied to an NRZI modulation circuit. Here, redundancy bits are selected dependent on whether code inversion is necessary between the blocks to which the redundancy bits are to be inserted, and on the state of the last part of the immediately preceding block. More specifically, the redundancy bits are selected so as to reduce DC component of the NRZI modulated recording signal and not to reduce Tmin.
Further, Japanese Patent Publication No. 5-34747 discloses a coding scheme in which rule of translation, i.e. a look-up table for translating a data sequence to RLL codes is adjusted in accordance with arrangement of data sequence, whereby Tmin of 1.5T, Tmax of 4.5T and Lc of 5T can be attained.
Japanese Patent Publication No. 4-77991 discloses a technique for reducing DC component of the recording signal after NRZI modulation and to enlarge Tmin. According to this published application, datawords each of 8 bits are successively cut out from an input data sequence, and each dataword is translated to codewords each of 14 bits. Translation is performed such that in the translated code sequence, the number of bits of xe2x80x9c0xe2x80x9d is at least 1 and at most 8 between a bit xe2x80x9c1xe2x80x9d and another bit xe2x80x9c1xe2x80x9d. There are two tables prepared for translating a dataword of 8 bits to a codeword of 14 bits, and dependent on the DSV at the end of the codeword that is translated immediately before, a codeword of either of the tables is selected. More specifically, selection is made to reduce DC component of the recording signal after NRZI modulation.
Further, Japanese Patent Laying-Open No. 6-311042 discloses a technique for sufficiently reducing DC component of the recording signal after NRZI modulation and to improve recording density DR (density ratio) by enlarging Tmin. According to this Laid-Open application, datawords each of 8 bits are successively cut out from an input data sequence, and each dataword is translated to a codeword each of 17 bits. The translation is performed such that in the translated code sequence, the number of bits xe2x80x9c0xe2x80x9d existing between a bit xe2x80x9c1xe2x80x9d and another bit xe2x80x9c1xe2x80x9d is at least 2 and at most 9.
The aforementioned codeword of 17 bits is obtained by adding redundancy bits of 2 bits, to a code of 15 bits corresponding to the dataword of 8 bits. According to the aforementioned Japanese Patent Laying-Open No. 6-311042, two tables specifying correspondence between the datawords of 8 bits each to codes of 15 bits each are prepared, and three different types of redundancy bits each of 2 bits are prepared. By a 17 bit codeword selected based on the DSV at the end of the data translated immediately before from six different codewords obtained by the combination of these two tables and three different types of redundancy bits, said dataword of 8 bits is replaced. More specifically, said 8 bit dataword is replaced by a 17 bit codeword selected to reduce the DC component of the recording signal after NRZI modulation.
In the techniques disclosed in the aforementioned applications, in order to suppress DC component or low frequency component of the recording signal, a technique of adding redundancy bits or preparing a plurality of translation tables to select an optimal translation table in accordance with the input dataword, for example, are used. Accordingly, the above described condition on xe2x80x9cdxe2x80x9d or xe2x80x9ckxe2x80x9d is become less severe, resulting in an inconvenience of Tmin becoming smaller or Tmax becoming larger. As the number of bits of the codeword increases, Tw becomes smaller, causing a problem that the minimum resolution becomes lower.
Therefore, a main object of the present invention is to provide a digital modulation circuit, a digital modulation method, a digital demodulation circuit and a digital demodulation method allowing sufficient suppression of DC component and low frequency component of the recording signal.
Another object of the present invention is to provide a digital modulation circuit, a digital modulation method, a digital demodulation circuit and a digital demodulation method allowing sufficient suppression of DC component and low frequency component of the recording signal while preventing reduction of Tmin or enlargement of Tmax.
A still further object of the present invention is to provide a digital modulation circuit, a digital modulation method, a digital demodulation circuit and a digital demodulation method allowing improvement of resolution by enlarging Tw, while sufficiently suppressing DC component and low frequency component of their recording signal.
A still further object of the present invention is to provide a digital modulation circuit, a digital modulation method, a digital demodulation circuit and a digital demodulation method allowing reduction in error in reproduction and reduction of error propagation in reproduction.
The present invention provides a method of digital modulation utilizing m-n modulation system in which an arbitrary sequence of m bits in translated to in one to one correspondence to an arbitrary sequence of n bits where (nxe2x89xa7m), for m-n modulating, using every m bits of the input digital data as a unit of code modulation, every m bits to n bits of modulated data, in which at the head of a p-bit input block data consisting of a prescribed number of data translation units (t bits), each of a plurality of different types of t bit data is multiplexed as initial data, whereby a plurality of different types of pre-translation block data are produced. For each of the plurality of different types of pre-translation block data, t bits at the head of the pre-translation block data and immediately succeeding t bits are subjected to exclusive OR operation, the immediately following t bits are replaced by the result of operation, the replaced t bits and immediately following t bits are subjected to exclusive OR operation, and the immediately following t bits are replaced by the result of operation. Thereafter, in the similar manner, convolution operation including the exclusive OR operation and the replacement operation is executed until the end of the pre-translation block data, whereby translated block data are produced from respective pre-translation block data. DC components of respective modulated block data obtained by m-n modulation of the plurality of different types of translated block data are compared with each other, initial data corresponding to that modulated block data which has a small absolute value of the DC component is selected, and m-n modulation block data which corresponds to the pre-translation block data on which the selected initial data has been multiplexed is produced.
More preferably, said selection is performed by specifying the modulated block data having the minimum absolute value of the accumulated value of the DC component at the last bit of the modulated block data.
Further, said selection is performed by specifying the modulated block data having the minimum absolute value of maximum amplitude of the accumulated value of DC component of the modulated block data.
According to another aspect, the present invention provides a digital modulation circuit utilizing m-n modulation system in which an arbitrary sequence of m bits is translated in one to one correspondence to an arbitrary sequence of n bits (where (nxe2x89xa7m), for m-n modulating, using every m bits of the input digital data as code modulation unit, every m bits to modulated data of n bits each, wherein at the head of a p-bit input block data consisting of a prescribed number of data translation units (t bits), each of a plurality of different types of t bit data is multiplexed as initial data, and a plurality of different types of pre-translation block data are produced by a multiplexing circuit. For each of the plurality of different types of pre-translation block data, t bits at the head of the pre-translation block data and immediately following t bits are subjected to exclusive OR operation, and the immediately following t bits are replaced by the result of operation. The replaced t bits and immediately following t bits are subjected to exclusive OR operation, and the immediately following t bits are replaced by the result of operation, and thereafter, in the similar manner, convolution operation including the exclusive OR operation and the replacement operation is executed until the end of the multiplexed block, so that from each pre-translation block data, a translated block data is produced. The DC components of respective modulated block data obtained by m-n modulation of the plurality of different types of translated block data are calculated by a calculating circuit, magnitude of absolute values of respective DC components are compared by a comparing circuit with each other, and initial data corresponding to the modulated block data having small absolute value of the DC component is selected by a selecting circuit, and m-n modulated block data corresponding to the pre-translation block data on which the selected initial data has been multiplexed is produced by the modulation circuit.
More preferably, the selecting circuit selects that initial data which corresponds to the modulated block data having minimum absolute value of the accumulated value of the DC component at the last bit of the modulated block data.
Further, more preferably, the selecting circuit selects that initial data which corresponds to the modulated block data having minimum absolute value of maximum amplitude of the modulated block data.
Further, a memory for storing respective modulated block data is provided, and modulation circuit reads the translated block data corresponding to the initial data selected by the selecting circuit from the memory for m-n modulation.
Further, the input block data is stored in the memory, the input block data is read from the memory, the initial data selected by the selecting circuit is multiplexed by a second multiplexing circuit, for the pre-translation block data output from the second multiplexing circuit, t bits at the head and immediately following t bits are subjected to exclusive OR operation, the immediately following t bits are replaced by the result of operation, the replaced t bits and immediately following t bits are subjected to exclusive OR operation, the immediately following t bits are replaced by the result of operation and, thereafter, convolution operation including the exclusive OR operation and the replacement operation is executed until the end of the pre-translation block data, translated block data is produced from the pre-translation block data by a second data translating circuit, and the modulation circuit performs m-n modulation on the translated block data output from the second data translating circuit.
Further, according to another aspect, the present invention provides a method of digital demodulation in which every n bits of input digital data as a code demodulation unit are subjected to n-m modulation to modulated data of m bits each (where nxe2x89xa7m), wherein demodulated block data consisting of a prescribed number of data reverse translation unit (t bits) are successively produced, t bits at the head of the demodulated block data and immediately following t bits are subjected to exclusive OR operation and the t bits at the head are replaced by the result of operation. The said immediately following t bits and t bits immediately following the immediately following t bits are subjected to exclusive OR operation, and the immediately following t bits are replaced by the result of operation, and thereafter, in the similar manner, convolution operation including the exclusive OR operation and the replacement operation is executed until the end of the demodulated block data, whereby reverse translated block data are produced.
Further, according to a further aspect, the present invention provides a digital demodulation circuit in which every n bits of input digital data as a code demodulation unit are n-m demodulated by a demodulation circuit to m bits (where (nxe2x89xa7m) demodulated data, demodulated block data consisting of a prescribed number of data reverse translation units (t bits) are successively produced, and each data reverse translation unit is held by a latch circuit until replacement operation of the data reverse translation unit is completed. By a reverse translation circuit, t bits at the head of the demodulated block data and immediately following t bits are subjected to exclusive OR circuit, t bits at the head are replaced by the result of operation, the immediately following t bits and t bits immediately following the immediately following t bits are subjected to exclusive OR operation, and said immediately following t bits are replaced by the result of operation and thereafter, in the similar manner, convolution operation including exclusive OR operation and replacement operation is executed until the end of the demodulated block data, and reverse-translated block data are produced.
Further, according to a still further aspect, the present invention provides a method of digital modulation utilizing m-n modulation system in which an arbitrary sequence of m bits is translated in one to one correspondence to an arbitrary sequence of n bits (where nxe2x89xa7m), for n-m modulating, using every m bits of input digital data as a code modulation unit, every m bits to modulated data each of n bits, wherein from immediately preceding translated demodulation code unit or initial data number and from pre-translation demodulation code unit data, translation is performed using a translation table, to translated modulation code unit data, whereby a plurality of different types of block data are produced, DC components of the plurality of different types of block data are compared with each other, and the block data having small absolute value of the DC component is subjected to m-n modulation.
Further, according to a still further aspect of the present invention, at the head of an input block of p bits which is an integer multiple of t bits cut out from an input bit stream, each of a plurality of different types of initial data of t bits is multiplexed by a multiplexing circuit, whereby a plurality of different types of multiplexed blocks are generated, for each of the plurality of different types of multiplexed blocks, t bits at the head of the multiplexed block and immediately following t bits are subjected to exclusive OR operation by an operating circuit, the immediately following t bits are replaced by the result of operation, the replaced t bits and immediately following t bits are subjected to exclusive OR operation, and the immediately following t bits are replaced by the result of operation. Thereafter, in the similar manner, convolution operation including exclusive OR operation and replacement operation is executed until the end of the multiplexed block. The DC component of the plurality of different types of translated blocks produced by the processing of the convolution operation circuit are calculated by a DC component calculating circuit, magnitude of absolute values of respective DC components are compared with each other, and the translated block which has the minimum magnitude of the absolute value is selected by a selecting circuit and output externally.
According to a still further aspect, the present invention provides a digital modulation circuit in which at the head of an input block of which bit number is an integer multiple of t bits cut out from an input bit stream, each of a plurality of different types of t-bit initial data is multiplexed by a multiplexing circuit, whereby a plurality of different types of multiplexed blocks are produced. By a first assigning circuit, the initial data is assigned to a preceding variable at first, and secondly and thereafter, successively applied t-bit translated data are assigned, by a second assigning circuit, current data read t bits by t bits successively from the head excluding the initial data of the multiplexed block are assigned to the current variable, and the preceding variable and the current variable are subjected to exclusive OR operation by a first operating circuit and translated data is produced. The translated data is applied to the first assigning circuit, the current data read successively from the head except the initial data of the multiplexing block are replaced by the translated data by the second operating circuit, by the processing of the first and second assigning circuits and first and second operating circuits, DC components of the plurality of different types of translated blocks produced from the plurality of different types of multiplexed blocks are calculated by a DC component calculating circuit, absolute values of respective DC components are compared with each other, and that translated block which has the minimum magnitude is selected by a selecting circuit and output externally.
Further, according to a still further aspect, the present invention provides a digital modulation circuit in which input blocks of which bit number is an integer multiple of t bits are successively cut out from an input bit stream by an input block producing circuit, a plurality of different types of initial data of t bits are produced by an initial data producing circuit, initial data is assigned to the preceding variable by a first assigning circuit at first, and secondary and thereafter, t bits of translated data applied successively are assigned, and by the second assigning circuit, current data read t bits by t bits successively from the head of the input block are assigned to the current variable. The preceding variable and the current variable are subjected to exclusive OR operation by the first operating circuit and translated data is produced, the translated data is applied to the first assigning circuit, and the current data read successively from the head of the input block is replaced by the translated data, by the second operating circuit. By the processings of the first and second assigning circuits and the first and second operating circuits executed on the plurality of different types of initial data, a plurality of different types of translated blocks are produced, of which DC components are calculated by the DC component calculating circuit, absolute values of respective DC components are compared with each other, and that translated block which has the minimum magnitude is selected by the selecting circuit and output externally.
Further, more preferably, the translated block is modulated to a recording signal block of a prescribed system by the modulation circuit, the DC component calculating circuit calculates each of the DC components when the plurality of different types of translated blocks are modulated to recording signal blocks respectively, and the selecting circuit output the selected translated block to the modulation circuit.
Further, more preferably, the DC component calculating circuit calculates the accumulated value of the DC components of the translated blocks.
According to a still further aspect, the present invention provides a digital modulation method in which at the head of an input block of which number of bits is an integer multiple of t bits cut out from an input bit stream, each of a plurality of different types of t-bit initial data is multiplexed, so that a plurality of different types of multiplexed blocks are produced, for each of the plurality of different types of multiplexed blocks, t bits at the head of the multiplexed block and immediately following t bits are subjected to exclusive OR operation, the immediately following t bits are replaced by the result of operation, the replaced t bits and immediately following t bits are subjected to exclusive OR operation and the immediately following t bits are replaced by the result of operation. Thereafter, in the similar manner, convolution operation including exclusive OR operation and the replacement operation is executed until the end of the multiplexed block, DC components of the plurality of different types of translated blocks produced by the convolution operation are calculated, magnitudes of absolute values of respective DC components are compared with each other, and that translated block which has the minimum magnitude is selected and externally output.
More preferably, comparison of the DC components is performed based on the DC components when the plurality of different types of translated blocks produced by the convolution operation are modulated to the recording signal blocks of the prescribed recording system. The DC component to be calculated is the accumulated value of the DC components at the last bit of the translated block. Further, the DC component to be calculated is a maximum amplitude of the accumulated value of the DC components of the translated block.
Further, according to a still further aspect, the present invention provides a digital demodulation circuit in which input block of a prescribed number of bits starting with initial data of t bits is cut out from an input bit stream, t bits at the head of the input block and immediately following t bits are subjected to exclusive OR operation, and the t bits at the head are replaced by the result of operation. The immediately following t bits and t bits immediately following the immediately following t bits are subjected to exclusive OR operation, the immediately following t bits are replaced by the result of operation, and thereafter, in the similar manner, convolution operation including exclusive OR operation and replacement operation is executed until the end of the input block, whereby reverse-translated block of the input block is produced.
According to a still further aspect, the present invention provides a digital demodulation method in which an input block of a prescribed bit number starting with initial data of t bits is cut out from an input bit stream, t bits at the head of the input block and immediately following t bits are subjected to exclusive OR operation, the t bits at the head are replaced by the result of operation, the immediately following t bits and t bits immediately following the immediately following t bits are subjected to exclusive OR operation, and said immediately following t bits are replaced by the result of operation and, thereafter, in the similar manner, convolution operation including exclusive OR operation and replacement operation is executed until the end of the input block, whereby reverse-translated block of the input block is produced.
Preferably, the number of bits t of the initial data is selected to be in the range of 2 bitsxe2x89xa6txe2x89xa68 bits, assuming that the input block has the data length of 80 bytes.
Further, the number of bits t of the initial data and the number of bits p of the input block which is an integer multiple of the bit number t are selected to satisfy the relation of 0.003xe2x89xa6t/pxe2x89xa60.015.